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Raytheon
Signetics
Signetics - TTL III 54H00 and 74H00
The 54H00/74H00 logic family is high speed TTL III. These transistor-transistor logic circuits were designed for general purpose applications. They have good external noise immunity and high fan-out.
Select a Series Below
10K ECL DevicesBiploar LSI 2900 - 3000 & 8X00
Bipolar Memory 82S00, 82HS00, 82LS00
Controller/Peripheral 68172
DTL 100 - 400 & CS700, S8000
Linear 500 & 1400
Low Power Schottky TTL 54LS00 - 74LS00
LSI 9400
Schottky TTL 54S00 - 74S00
TTL 5400 - 7400
TTL 8200 & 8H00
TTL 8800
TTL 9000
TTL III 54H00 and 74H00
TTL Interface 8T00
Utilogic II 300
| Original # | Lansdale # | |
| N74H00 | SL74H00 | |
| N74H01 | SL74H01 | |
| N74H20 | SL74H20 | |
| N74H30 | SL74H30 | |
| N74H52 | SL74H52 | |
| S54H00 | SL54H00 | |
| S54H01 | SL54H01 | |
| S54H20 | SL54H20 | |
| S54H30 | SL54H30 | |
| S54H52 | SL54H52 |
| Package Types |
| C - 14-LEAD DUAL INLINE (1/4" X 3/4") |
| D - 14-LEAD FLAT PACK (1/4" X 3/8") |
| E - 16-LEAD DUAL INLINE (1/4" X 7/8") |
| F - 16-LEAD FLAT PACK (1/4" X 3/8") |
| Rating | Value | Unit |
| Supply Voltage - VCC | +7.0 | V |
| Input Voltage - Vin | +5.5 | V |
| Output Voltage - Vout | +5.5 | V |
| Operating Temperature Range | -55 to +125 | |
| Array |
| Quad 2-Input Positive NAND Gate |
| Quad 2-Input Positive NAND Gate (O.C.) |
| Quad 2-Input Positive AND Gate |
| Triple 3-Input Positive NAND Gate |
| Triple 3-Input Positive AND Gate |
| Dual 4-Input Positive NAND Gate |
| Dual 4-Input AND Gate |
| Dual 4-Input NAND Gate (O.C.) |
| 8-Input Positive NAND Gate |
| Dual 4-Input Positive NAND Buffer |
| 4-Wide 2-2-2-3 Input AND-OR-INVERT Gate |
| Expandable 2-2-2-3 Input AND-OR-INVERT Gate |
| Expandable 2-2-2-3 Input AND-OR-INVERT Gate |
| Expandable 2-Wide 4-Input AND-OR-INVERT Gate |
| Dual 4-Input Expander |
| Triple 3-Input Expander for AND-OR Gates |
| 4-Wide 3-2-2-3 Input Expander for AOI Gates |
| J-K Master-Slave Flip-Flop |
| J-K Master-Slave Flip-Flop |
| Dual J-K Master-Slave Flip-Flop |
| Dual Type D Edge-Triggered Flip-Flop |
| Dual J-K Master-Slave Flip-Flop |
| J-K Edge-Triggered Flip-Flop |
| J-K Edge-Triggered Flip-Flop with AND Inputs |
| Dual J-K Edge-Triggered Flip-Flop |
| Dual J-K Edge-Triggered Flip-Flop |
| Dual J-K Edge-Triggered Flip-Flop |
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